1. Field of the Invention
The present invention relates to an analog-to-digital converter either of the type that converts the whole bits together, or of the type that converts only several bits at one time.
2. Description of the Related Art
FIG. 5 is a schematic diagram showing a conventional analog-to-digital converter (hereinafter may be referred to just as an A/D converter), namely an 8-bit flash type converter. In the figure, reference numeral 1 denotes a ladder resistance for variably generating 256 types of reference voltages, numeral 2 denotes an amplifier group composed of 256 amplifiers, each of which compares the analog voltage of an input analog signal that is to be A/D converted with the reference voltages, whenever an analog signal is fed thereto, and numeral 3 denotes an encoder for generating an 8-bit digital code corresponding to the results of the comparison made in each of the 256 amplifiers configuring the amplifier group 2.
The operation of the conventional A/D converter is as follows.
Conventionally, there have been provided various analog-to-digital converters for converting an analog signal to a digital signal at high speed, such as a flash A/D converter that converts the whole bits together, and the one that converts only several bits at one time and so on.
As these types of A/D converters convert the whole bits together or a plurality of bits at one time, they require as many amplifiers as the n-time multiplied value of 2, wherein n corresponds to the number of bits to be converted, so that in the case of an 8-bit flash A/D converter for example, as many as 28, namely 256 amplifiers are required.
In the flash A/D converter shown in FIG. 5, an analog signal is converted to a digital signal in the following manner.
First of all, when the ladder resistance 1 generates arbitrary reference voltages, the amplifier group 2 made of 256 amplifiers externally inputs an analog signal that is to be A/D converted, and compares the thus generated reference voltages with the analog voltage of the input analog signal, and thereafter outputs the results of the comparison made in each of the 256 amplifiers configuring the amplifier group 2 to the encoder 3.
When the encoder 3 receives the results of the comparison made in these 256 amplifiers, it generates an 8-bit digital code corresponding to the results of the comparison, and then outputs externally the thus generated digital code as a digital signal representing the result of the A/D conversion.
It is to be noted that although it is required to test the amplifier group 2 or the encoder 3 before delivering the A/D converter, if the test is conducted in such a manner that the analog voltage of an input analog signal is varied gradually, and the digital signal output from the encoder 3 is checked, malfunction of the 256 amplifiers configuring the amplifier group 2 (for example that of the transistors configuring the 256 amplifiers) can be detected.
Since the conventional A/D converter is configured as such, if the digital signal output from the encoder 3 is checked by gradually varying the analog voltage of an input analog signal, malfunction of the 256 amplifiers configuring the amplifier group 2 can be detected. However, as the result of the comparison made in the amplifier group 2 cannot be directly observed under the condition that the encoder 3 is not functioning properly, the judgement as to whether the amplifiers are properly functioning is not perfectly reliable.
In addition, the encoder 3 is normally provided with a built-in error correction circuit, which corrects output values fed from the amplifiers in the case where the outputs of one or more than one amplifiers are inverted to be an unexpected value due to a noise or the like. Subsequently, in the case where the encoder 3 including an error correction circuit therein is employed, even if the digital signal output from the encoder 3 is checked, the judgment as to whether the amplifiers configuring the amplifier group are functioning properly is not perfectly reliable due to this correction.
It is to be noted that apart from this conventional example, microcomputers, which does not detect malfunction of the amplifier group 2 within the A/D converter, but detects the overall entire A/D converter have been disclosed in Japanese Patent Applications Laid-Open No. 3-1616, and also No. 58-60824.
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide an A/D converter that is capable of properly evaluating the function of the amplifiers configuring the amplifier group provided therein.
In order to achieve the above object, an analog-to-digital converter according to a first aspect of the present invention is constructed in such a manner that it comprises a comparison-result output means which, when executing the test of the amplifier group, inputs all the results of the comparison made in each of the amplifiers configuring the amplifier group together, and sequentially outputs the thus received results per one bit for each time.
In the above construction, the comparison-result output means is composed of a shift register that first inputs all the results of the comparison made in the amplifier group together, and thereafter outputs the thus input results of the comparison made in a plurality of amplifiers per one bit for each time in synchronization with clock signals.
Also in the above construction, the comparison-result output means may be composed of a counter for designating an amplifier, the result of the comparison made in which is to be output among all the amplifiers configuring the amplifier group, and a selector for outputting the result of the comparison made in the amplifier designated by the counter after inputting all the results of the comparison made in the amplifier group together.
An analog-to-digital converter according to another aspect of the present invention is constructed in such a manner that it comprises: an amplifier group for comparing a plurality of reference voltages and an analog voltage of an input analog signal, which amplifier group being composed of a plurality of amplifiers, an encoder for generating a digital code corresponding to all the results of the comparison made in each of the amplifiers of the amplifier group, and an input/output means which, when executing the test of the amplifier group, inputs all the results of the comparison made in each of the amplifiers together, and thereafter sequentially outputs the thus input results of the comparison per one bit for each time, whereas when executing the test of the encoder, electrically separates the encoder from the amplifier group, and sends test codes related to the thus input comparison results of the amplifier group to the encoder.
In the above construction, the input/output means is composed of: a shift register which, when executing the test of the amplifier group, inputs all the results of the comparison made in each of the amplifiers together, and thereafter sequentially outputs the thus input results of the comparison per one bit for each time in synchronization with clock signals, whereas, when executing the test of the encoder, inputs the test codes per one bit in synchronization with clock signals, and thereafter outputs the thus input test codes all at once to the encoder, and a connection switching means which, when executing the test of the amplifier group, connects the amplifier group to the shift register, whereas, when executing the test of the encoder, electrically separates the encoder from the amplifier group, and connects the encoder to the shift register instead.
Also in the above construction, the input/output means may be composed of: a counter which, when executing the test of the amplifier group, designates an amplifier, the result of the comparison made in which is to be output among all the amplifiers configuring the amplifier group, whereas, when executing the test of the encoder, designates a bit, a test code to which is to be input, a selection means which, when executing the test of the amplifier group, outputs the result of the comparison made in the amplifier designated by the counter after inputting all the results of the comparison made in each of the amplifiers together, whereas, when executing the test of the encoder, sequentially inputs the test codes of the bits designated by the counter, and thereafter outputs those test codes all at once, and a connection switching means which, when executing the test of the amplifier group, connects the amplifier group to the selection means, whereas when executing the test of the encoder, electrically separates the encoder from the selection means, and connects sad encoder to the selection means instead.